| 1 |
An area efficient data flip flop with low power and delay with conditional pulse enhancement scheme |
Edit
Delete |
| 2 |
Design of New Low-Power and Area Efficient Full Adder For Arithmetic Applications, International Jou |
Edit
Delete |
| 3 |
Design of New Double-Tail Comparator with Low-Voltage Low-Power and Area Efficient, International J |
Edit
Delete |
| 4 |
Design and Analysis of Low-Voltage Low-Power Double tail Comparator And Implementation of 3bit, Fla |
Edit
Delete |
| 5 |
Design of New Dual Edge Triggered Sense Amplifier Flip-Flop with Low Area and Power Efficient, Inter |
Edit
Delete |
| 6 |
Design of a New Dual Dynamic Flip-Flop with Low Power and Low Area, International Journal of Engine |
Edit
Delete |
| 7 |
Design of a Low Power and Area Efficient Flip-Flop with Embedded Logic Module, IOSR Journal of Elect |
Edit
Delete |
| 8 |
Analysis on Linear Planar Antenna in X-Band Range, IJETER, Volume 5, Issue 12, December (2017) |
Edit
Delete |